The continuous demand for high speed integrated circuits (ICs) results in the continuous increase of transistor density and decrease of the feature size in the past two decades. As a technology to print circuit patterns with submicron features, and to place those features on a silicon substrate with ever higher recision, optical lithography is the cornerstone of modern IC manufacturing. Its development has been the primary factor driving improvements of IC technology for several decades. According to the 15-year roadmap for lithography requirement in the 2001 ITRS, optical lithography is projected to remain the dominant technology option at least in the next decade until the appearance of the next-generation microlithography technology. The critical dimension (CD)—the minimum feature size that can be defined by optical lithography—has been reduced to 130 nm in 2001 and is projected to have a 30% reduction in every three years.
Following Moore's Law, chip feature sizes are shrinking at a faster clip than resolution improvements enabled by developments in optical lithography equipment. In addition to enhancements in materials and equipment, resolution enhancement techniques (RETs) and new design methodologies are required to facilitate the projected reduction in feature size. It was the application of RETs in the past decade, coupling with the improvement in system equipment, that helped improve resolution of optical lithography systems to the current 100-nm level. However, the improvement of optical lithography equipment come to a halt due to the extreme technology challenges in developing the next generation optical imaging system with a smaller illumination wavelength. Applying highly-optimized strong-RETs is the only viable solution for all future optical technology nodes below 100 nm. Invented in 1982, strong-RETs based on two-beam imaging provided a solution for today's challenge two decades ago. However, although the achieved resolution can be doubled, challenges associated with the two-beam imaging, not only for electronic design automation (EDA) solutions, but also for manufacturing cost, prevented it from being implemented in the past.
If strong-RETs are carefully optimized, they will provide adequate resolution for sub-100 nm nodes and afford sufficient process latitude. Physical design constraints required by strong-RETs imposed on circuit design and cannot be enforced through conventional design flows. The RET-embedded design flow, which is required by the strong-RET-imposed layout restrictions to guarantee layout-compliant designs, is significantly more complicated than conventional flow and requires a design and process integration (DPI). RET-compliant design tools are put into the hands of the designers in the new flow. That increases difficulties in EDA software design and requires layout designers to have a good knowledge of the strong-RETs used in a process. Furthermore, the process-specific nature of RET-specific optimization in the new flow does not ensure design compatibility with future lithography solutions. All of these increase design cost for sub-100 nm technology nodes as well as manufacturing cost which has been pushing to an alarming level because of increasingly complicated fabrication process with highly-optimized RETs. An easily established and non-RET-specific process will be more attractive for circuit designers.
To overcome the above-mentioned challenges, manufacturability should be taken in consideration during the design stage. The term “Design for Manufacturability” (DFM) has been introduced in the industry. The manufacturability includes low manufacturing cost, compatibility among different RET approaches (non-RET-specific), simplicity for process optimization, and ease for migration of designs into future technology nodes.
To achieve these objectives, fabrication-friendly layout, in which circuit pattern configurations are limited to allow lithography optimization, is introduced. Designs with the introduced radical layout restrictions can be compliant for all strong-RETs, and therefore, free layout designers from RET-compliant layout tools. A major benefit of fabrication-friendly layout is the dramatic simplification of the layout methodology. The introduced radical layout restrictions can be easily embedded into the conventional design rules and keep the conventional design flow and EDA solutions still workable for the sub-100 nm technology nodes. The non-RET-specific design also simplifies the process optimization and ensures layout compatibility with future lithography solutions.
However, there is no “free lunch” in the world. As a trade-off between design flexibility and manufacturability, fabrication-friendly layout decreases the flexibility in physical design. Although the features can be designed smaller and packed closer, the excessive lithography friendliness in fabrication-friendly layout may be so restrictive on layout design that circuit area increases unacceptably. It should be studied extensively to seek a fine balance between design flexibility and manufacturability.
Therefore, the application of fabrication-friendly layout depends on the type of applications. For low-volume product market, such as application-specific integrated circuits (ASICs), keeping the manufacturing cost in an acceptable region for the sub-100 nm technology nodes is more critical than keeping a high improvement ratio of product performance. On the other hand, for performance-dominant products, such as microprocessor units (MPUs), or high-volume products, such as Dynamic Random Access Memory (DRAM), design and manufacturing cost is not the first factor in consideration. Therefore, simplifying the design flow and lithography optimization procedure, fabrication-friendly layout offers a possibility to decrease design and manufacturing cost for sub-100 nm technology nodes and becomes a very attractive option for ASIC foundries.
Contact level is one of the most difficult parts of a lithography process and has the biggest cost weighting. In the application of fabrication-friendly contacts in standard cells, one of the core blocks of cell-based application-specific integrated circuits (ASICs), the contact should the placed unrestrictedly in the height direction while regularly in the width direction with 1½ transistor pitch as the grid pitch. Transistor pitch, also called a “contacted pitch,” is the minimum pitch between two gates with a contact between them. Because MOSFETs in a standard cell are placed one by one in the width direction, the width of a cell is roughly determined by the product of the transistor pitch and the number of the transistors. Reduction of the contact size gets a reduced transistor pitch and leads to a decrease of the cell width. On the other hand, it is the metal-1 pitch instead of the contact pitch or size that determines the height of a standard cell. The minimum pitch and size of contacts in the height direction is not critical for the height of standard cells. Applying a regular placement on the contacts in the height direction cannot help to decrease the height of a standard cell except for an increased difficulty in the layout compaction.
However, there are several difficulties to apply such a regularly-placed layout on a standard cell. First, although many advanced lithography approaches for fabrication-friendly contacts have been proposed in the last few years [BT02], pushing the revolution to about its minimum value, all of these approaches place contacts regularly in both directions at the same time [BT02, WJ03]. Second, although the resolution (single-exposure) can be improved by a regularly-placed layout, the desired grid pitch (1½ transistor pitch) is still smaller than the improved resolutions of a contact layer. Although multiple exposures can be introduced to fabricate the new layout [SN96,WJ03], it increases the cost and decreases the throughput. The lithographic approach should be selected carefully to decrease the number of extra masks and exposures.